1. Field of the Invention
The present invention relates generally to field effect transistors such as CMOS transistors. More particularly, the present invention relates to a method for forming field effect transistors with stressed channel regions which provide increased drive current capability among other benefits.
2. Background Description
Field effect transistors such as CMOS transistors are widely used in the electronics industry. Field effect transistors (FETs) are employed in almost every electronic circuit application, such as signal processing, computing, and wireless communications. There is constantly a demand for improved field effect transistor performance. Performance metrics that may be of interest include switching speed, on-state current capability, and on-state to off-state current ratio. These metrics tend to be improved by increasing the charge carrier mobility of the FET. Hence, researchers have been searching for techniques to increase the charge carrier mobility of FETs.
It has been discovered that mechanical stress applied to the current channel of a FET can increase the charge carrier mobility. For example, Hamada et al. in “A New Aspect of Mechanical Stress Effects in Scaled MOS Devices” in IEEE Transactions on Electron Devices, Vol. 38, No. 4, April 1991 describes the results of experiments in which performance characteristics of P-type FET (PFET) and N-type FET (NFET) MOS transistors were measured as a function of mechanical stress. It was reported that longitudinal (in the direction of current flow) compression in PFET devices increased carrier mobility, and longitudinal tension in NFET devices increased carrier mobility.
However, incorporating mechanical stress into microfabricated FETs and CMOS devices has proven difficult. In the past, researchers have simply flexed the transistor substrate. However, this technique is not practical for mass producing integrated circuits. One significant problem with employing stress is that PFET and NFET devices require opposite stress. Also, the technique for producing stress in the devices must be compatible with present FET manufacturing practices and packaging techniques.
It would be an advance in the art to provide FETs having stressed channel regions. It would be particularly beneficial to be able to make PFET and NFETs having opposite stresses on the same substrate so that both PFET and NFETs are enhanced. Also it would be an advance to be able to make FETs with strained channel regions in a conventional FET fabrication process.